You're right in part about it not being a RISC versus CISC issue. The issue lies not in the instruction set used, but rather in the associated processor structuring. (I.e. 68k used CISC-style adressing, while PPC uses RISC-style addressing as seen in for example the Power, MIPS, UltraSparc, Alpha or Itanium families. Which affects both memory handling and perifernalia handling.)
In fact, the x86 are practically RISC nowadays if you look at their internal workings. They translate CISC instructions to internal microinstructions that are very RISC-like, especially Intel. AMD on the other hand have gained much in their superior FPU and branch prediction, but are closer to the original CISC.
(It can also be noted that the RISC 68k family had a more extensive instruction set than the CISC x86...)
Last edited by liorean; 05-21-2004 at 09:19 PM..