Verilog Help!!!

[dbhakta]

I am getting an error with the 3rd from last line of code(assign statement)...can somebody help me out?


module Duty_Display(clk100, clkin, anodes, clkout100, SevenSeg);

output [7:0] SevenSeg;
output [3:0] anodes;
input clk100;
input clkin;
output clkout100;
reg [1:0] teller;
assign anodes[3:0] = 4'b1111;

[oracleguy]

In the future please also include the error message so people don't need to compile (or in this case synthesize) your code to get the error message.

You cannot put assign statements inside an always block, that is the reason there is an error. Either move it outside the always block or don't make it a continuous assignment.

Also you do realize that code is inferring a ton of latches right?